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1 p-0.3 07/09/10 block diagram PI2EQXDP101-A 1 to 1 displayport? redriver? features ? displayport? 1.1a operation at reduced bit rate (1.62gbps) and high bit rate (2.7gbps) ? jitter elimination circuits automatically adjust link via training path p re-emphasis, and output swing ? can support all 4 levels of output swing and 4 levels output pre-emphasis, as specifed in the displayport 1.1a spec. ? aux interception circuit only listens to the link training, but does not affect link training ? low insertion loss across the aux signal path (0.35db @1mbps) ? output can support dual mode dp by providing ddc signals across the aux_sink pins u sing cable detect pin from dp connector (pin 13), t he switch can toggle between dp and tmds mode. ? automatic power down state when hpd signal is low ? enters low power mode when no data signal is present ? dual power supply (1.5v and 3.3v) ? 2kv hbm esd protection ? 50 ohm output termination can be turned off when port is off p ort is turned off automatically when not needed ? package (pb-free & green available) 3 6-pin tqfn (zf) description the pi2eqxdp 101-a is a one input and one output displayport? redriver? that support a maxim um data rate of 2.7 gbps through each channel, which results in a total of 10.8gbps through-put. output level swing and output pre-emphasis and number of active lanes are controlled by decoding the aux command during link initialization. also, utilizing the hpd signals from each displayport port, the PI2EQXDP101-A can automatically enter power down state. or , if the graphics driver is of f and has no output signal, pericom s PI2EQXDP101-A can automatically enter low power mode, even if an active monitor is attached. out [3:0] ddc_scl/aux+ ddc_sda/aux- pre-emphasis equalizer bias hpd src cad src logics hpd_sink cad_sink aux_src+ aux_src- aux pass through ddc pass through aux ch interpreter register scl sda in [3:0] pin diagram (top-side view) in1+ in1- in2+ in2- gnd in3+ in3- out1+ out1- out2+ out2- out3+ out3- ddc_scl ddc_sda/aux- gnd hpd_sink cad_sink hpdsrc 1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 vdd33 ddc_sda out0+ out0- vdd15 cad aux_src+ aux_src- ddc_scl/aux+ gnd vdd15 vdd15 vdd15 in0+ in0- nc vdd15 10-0194
2 p-0.3 07/09/10 PI2EQXDP101-A 1 to 1 displayport? redriver? pin description pin # name i/o description 33 aux_src+ i/o aux positive channel on source side 32 aux_src- i/o aux negative channel on source side 12 cad output cable detect to source 14 cad_sink input cable detect from dp connector, with 200k-ohm pull-down. 34 ddc_scl i/o i 2 c scl clock on source side 31 ddc_scl/aux+ i/o aux channel positive when confgured as dp mode, i 2 c scl clock when confgured as tmds mode 35 ddc_sda i/o i 2 c sda data on source side 30 ddc_sda/aux- i/o aux channel negative when confgured as dp mode, i 2 c sda data when confgured as tmds mode 8, 18, 24, center pad gnd power ground 15 hpd_sink input hot plug detect from sink side, with 200k-ohm pull-down. 13 hpdsrc output hot plug detect to source 1 2 in0+ in0- input lane 0 data input, differential pair 3 4 in1+ in1- input lane 1 data input, differential pair 6 7 in2+ in2- input lane 2 data input, differential pair 9 10 in3+ in3- input lane 3 data input, differential pair 16 nc - no connect 28 27 out0+ out0- output lane 0 data output, differential pair 26 25 out1+ out1- output lane 1 data output, differential pair 23 22 out2+ out2- output lane 2 data output, differential pair 20 19 out3+ out3- output lane 3 data output, differential pair 5, 11, 17, 21, 29 vdd15 power power supply, 1.5v 5% 36 vdd33 power power supply, 3.3v 5% 10-0194
3 p-0.3 07/09/10 PI2EQXDP101-A 1 to 1 displayport? redriver? aux listener register assignment aux command are stored interpreted and stored in the registers, redriver will then be re-confgured by de- fault. registers do not have a power-on default state. address name description access 00100h link initialization feld aux link_bw_set : main link bandwidth setting = v alue x 0.27 gbps per lane bits 7:0 = link_bw_set for displayport version 1, revision 1a, only two values are supported. all other values are reserved. 06h = 1.62 gbps per lane 0ah = 2.7 gbps per lane source may choose either of the two link bandwidth as long as it does not ex- ceed the capability of displayport receiver as indicated in the receiver capabil- ity feld. r/w 00101h link initialization feld lane_count_set bits3:0 = lane_count_set 1h = one lane 2h = t wo lanes 4h = four lanes for one-lane confguration, lane0 is used. for 2-lane confguration, lane0 and lane1 are used. bits7:4 = reserved. read all 0s. r/w 00103h dpcd lane 0 status training_lane0_set link t raining control_lane0 bits1:0 = drive_current_set 00 C t raining pattern 1 w/ level 0 01 C t raining pattern 1 w/ level 1 10 C t raining pattern 1 w/ level 2 11 C t raining pattern 1 w/ level 3 bit2 = max_current_reached set to 1 when the maximum driven current setting is reached. note: support of programmable drive current is optional. for example if there is only 1 level, then program bits2:0 to 100 to indicate to the receiver that level 1 is the maximum drive current. support of independent drive current controlfor each lane is also optional. bit4:3 = pre-emphasis_set 00 = t raining pattern 2 w/o pre-emphasis 01 = t raining pattern 2 w/ pre-emphasis level 1 10 = t raining pattern 2 w/ pre-emphasis level 2 11 = t raining pattern 2 w/ pre-emphasis level 3 bit5 = max_pre-emphasis_reached r/w 00104h dpcd lane 1 status lane setting for lane 1. the defnition is the same as lane 0 r/w 00105h dpcd lane 2 status lane setting for lane 2. the defnition is the same as lane 0 r/w 00106h dpcd lane 3 status lane setting for lane 3. the defnition is the same as lane 0 r/w 10-0194
4 p-0.3 07/09/10 PI2EQXDP101-A 1 to 1 displayport? redriver? aux listener specifcation dp aux command interpreter will support native aux ch syntax. mapping of i 2 c onto aux ch syntax is not supported. aux command interpreter monitor aux channel from requester and replier for transactions and stored aux command from re- quester and reply command from replier that are related to the link settings. the data from the following addresses will be extracted and stored into internal registers for controlling the redriver signal level, lane count and pre-emphasis setting. 00101h lane_count_set 00103h training_lane0_set 00104h training_lane1_set 00105h training_lane2_set 00106h training_lane3_set application diagram hpd hpdsrc in pi2eqxdp101 redriver displayport transmitter dp connector cad ddc aux main link c cad_sink ddc/aux out c 10-0194
5 p-0.3 07/09/10 PI2EQXDP101-A 1 to 1 displayport? redriver? dc electrical characteristics (v dd 33 = 3.3v 5%, v dd 15 = 1.5v 5%, t a =0c to 85c) power supply characteristics symbol parameters condition min. typ. max. units i active_vdd15 current into v dd 15 when active 4-lanes operating at 2.7gbps 150 250 ma i standby_vdd15 current into v dd 15 when standby 10 ma i active_vdd33 current into v dd 33 when active 4-lanes operating at 2.7gbps 0.1 1.0 ma i standby_vdd33 current into v dd 33 when standby 0.1 ma p active total active power 4-lane, operating 2.7gbps 400 mw p standby total standby power 20 mw hpd_src, hpd_sink , cad, cad_sink, pin charaxteristics symbol parameters condition min. typ. max. units vih lvttl input high voltage 2 v vil lvttl input low voltage 0.8 v iih input high-level current 43 80 ua iil input low-level current 6 20 ua voh lvttl high level output voltage ioh=-8ma 2.4 v vol lvttl low level output voltage iol= 8ma 0.4 v aux_src , ddc_scl/aux+, ddc_sda/aux C pins (when confgured as scl and sda pins) symbol parameters condition min. typ. max. units iih input high-level current 43 80 ua iil input low-level current 6 20 ua storage temperature ........................................................ C65c to +150c supply voltage to ground potential ................................... C0.5v to +4.6v dc sig voltage ..........................................................C0.5v to v dd +0.5v current output ................................................................ -25ma to +25ma power dissipation continuous ....................................................... 500mw operating temperature .............................................................. 0 to +85c note: stresses greater than those listed under maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) aux_src , ddc_scl/aux+, ddc_sda/aux C pins (when confgured as aux pins) symbol parameters condition min. typ. max. units iih input high-level current 43 80 ua iil input low-level current 6 20 ua 10-0194
6 p-0.3 07/09/10 PI2EQXDP101-A 1 to 1 displayport? redriver? aux channel electrical specifcations symbol parameter conditions min nom max units v i aux unit interval 1mbps including overhead of mancester ii coding 0.4 0.5 0.6 s pre-charge pulses number of pre-charge pulses each pulse is a 0 in manches- ter ii code. 10 16 sync pulses number of sync pulses 16 v aux-diffp-p aux peak-to-peak voltage at a receiving device v aux-diffp-p = 2*|v aux+ C v aux- | 0.32 1.36 v aux atten aux attenuation with 100-ohm termination 1.5 2.0 db v auxp-dc aux+ dc voltage range 0 2.0 v v auxn-dc auxC dc voltage range 1.3 3.3 i aux_short aux short circuit current 90 ma c aux aux ac coupling capacitor the aux ch ac coupling capacitor placed on the display- port source 75 200 nf 10-0194
7 p-0.3 07/09/10 PI2EQXDP101-A 1 to 1 displayport? redriver? main link receiver (main rx) specifcations symbol parameters comments min. typ. max. units ui_high_rate unit interval for high bit rate (2.7 gbps / lane) range is nominal +/-350ppm. displayport link rx does not require local crystal for link clock generation. 370 ps ui_low_rate unit interval for low bit rate (1.62 gbps / lane) 617 ps v rx-diffp-p-hr differential peak-to-peak input voltage at rx package pins for high bit rate. informative. 120 1500 mv t rx-eye-medi- an-to- max-itter_chip maximum time between the jitter median and maximum deviation from the median at rx package pins 0.265 ui t rx-eye_conn minimum receiver eye width at r x -side connector pins note 1 0.25 ui t rx-eye_chip minimum receiver eye width at r x package pins note 1 0.22 ui t rx-eye-medi- an-to- max-jitter_chip maximum time between the jitter median and maximum deviation from the median at r x package pins note 1 0.39 ui v rx-dc-cm r x dc common mode voltage common mode voltage is equal to vbias_rx voltage 0 2.0 v z rx-dc dc input resistance 45 50 55 rl rx-diff differential return loss at 0.675ghz at r x package pins straight loss line between 0.675 ghz and 1.35 ghz 12 db differential return loss at 1.35ghz at r x package pins straight loss line between 0.675 ghz and 1.35 ghz 9 db l rx-skew- inter_pair lane-to-lane output skew at r x package pins maximum skew limit between different rx lanes of a displayport link. 5200 ps l rx-skew- intra_pair high- bit-rate lane intra-pair output skew at r x package pins for high bit rate maximum skew limit between d+ and d- of the same lane. 100 ps l rx-skew- intra_pair_re- duced-bit-rate lane intra-pair output skew at r x package pins for reduced bit rate maximum skew limit between d+ and d- of the same lane. 300 ps note: 1. for reduced bit rate (1- trx-eye_conn) specifes the allowable tj. trx-eye-median-to-max-jitter specifes the total allowable dj 10-0194
8 p-0.3 07/09/10 PI2EQXDP101-A 1 to 1 displayport? redriver? symbol parameters comments min. typ. max. units ui_high_rate unit interval for high bit rate (2.7 gbps / lane) high limit = +300ppm low limit = -5300ppm 370 ps ui_low_rate unit interval for low bit rate (1.62 gbps / lane) 617 ps v tx-diffp-p differential peak-to-peak output v oltage hbr, vdd15 = 1.5v voltage level 1 voltage level 2 voltage level 3 voltage level 4 340 340 510 690 1020 400 600 800 1200 1380 460 680 920 1380 mv v tx-preemp- ratio output pre-emphasis ratio hbr, vdd15 = 1.5v no pre-emphasis 3.5 db pre-emphasis 6.0 db pre-emphasis 9.5 db pre-emphasis 0.0 0.0 2.8 4.8 7.6 0.0 3.5 6.0 9.5 11.4 0.0 4.2 7.2 11.4 db t tx-eye_chip _high_rate minimum tx eye w idth at tx package pins for high bit rate 0.726 ui t tx-eye- median-to-max- jitter_chip__ high_rate maximum time between the jitter median and maximum deviation from the median at tx package pins for high bit rate 0.137 ui t tx-eye_chip _low_rate minimum tx eye w idth at tx package pins for reduced bit rate 0.82 ui t tx-eye- median-to-max- jitter_chip__ low_rate minimum tx eye w idth at tx package pins for reduced bit rate 0.09 ui t tx-rise_chip , t tx-fall_chip d+/d- tx output rise/fall time at tx package pins at 20%-to-80% 50 130 ps v tx-dc-cm tx dc common mode v oltage common mode voltage is equal to vbias_tx voltage shown in dif ferential w aveform 0 1.5 v v tx-ac-cm tx ac common mode v oltage measured at 1.62 ghz and 2.7 ghz (if supported), within the frequency tolerance range. t ime-domain measurement us- ing a spectrum analyzer. 20 mv i tx-short tx short circuit current limit t otal drive current of the trans- mitter when it is shorted to its ground. 50 ma r ltx-diff differential return loss at 0.675ghz at tx package pins straight loss line between 0.675 ghz and 1.35 ghz 12 db differential return loss at 1.35ghz at tx package pins straight loss line between 0.675 ghz and 1.35 ghz 9 db (continued) main link transmitter (main tx) specifcations 10-0194
9 p-0.3 07/09/10 PI2EQXDP101-A 1 to 1 displayport? redriver? symbol parameters comments min. typ. max. units l tx-skewin- ter_pair lane-to-lane output skew at tx package pins 2 ui l tx-skewin- tra_pair lane intra-pair output skew at tx pack- age pins 20 ps t tx-rise_fall _mismatch _chipdiff lane intra-pair rise-fall t ime mismatch at tx package pins. informative. d+ rise to d- fall mismatch and d+ fall to d- rise mismatch. 5 % c tx ac coupling capacitor all displayport main link lanes as well as aux ch must be ac coupled. ac coupling capacitors must be placed on the transmitter side. placement of ac coupling capacitors the receiver side is optional. 75 200 nf j total total output jitter 0.32 uip-p notes: 1. refer to pre-emphasis waveform. for embedded connection, support of programmable voltage swing levels is optional. 2. refer to pre-emphasis waveform for defnition of differential voltage. support of no preemphasis, 3.5 db and 6.0 db pre-emphasis is required. support of 9.5 db level is optional. for embedded connection, support of programmable preemphasis levels is optional. 10-0194
10 p-0.3 07/09/10 PI2EQXDP101-A 1 to 1 displayport? redriver? v d+ common mode voltage v_d+ - v_d- 0v v cm v diff v d- v diffp-p v diffp-p defnition of differential voltage and dif - ferential voltage peak-to-peak defnition of pre-emphasis v d+ v cm v diff v d- 1 st t bit 2 nd + t bit(s) v diff-pre pre-emphasis = 20 . log(v diff-pre /v diff ) output waveform (400mv, 0db pre-emphasis) output waveform (400mv, 6db pre-emphasis) output eye diagram (2.7gbps, 1200mv) output eye diagram (2.7gbps, 400mv) 10-0194
11 p-0.3 07/09/10 PI2EQXDP101-A 1 to 1 displayport? redriver? ordering information ordering code package code package description PI2EQXDP101-Azfe zf 36-contact, pb-free & green (tqfn) notes: ? thermal characteristics can be found on the company web site at www.pericom.com/packaging/ ? e = pb-free and green ? adding an x suffx = tape/reel pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com 1 description: 36-contact, very thin fine pitch quad flat no-lead (tqfn) package code: zf (zf36) document control #: pd-2023 revision: c date: 03/10/09 09-0143 packaging mechanicals: 36 contact, tqfn (zf) all trademarks are property of their respective owners. 10-0194

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